It is known that ternary material, such as gallium indium arsenide (GaInAs), shows great promise for use in semiconductor devices due to its high electron mobility and large saturation velocity. See an article in Appl. Phys. Letter 39(7), 1 Oct. 1981, pp. 569-572, by J. Degani, et al., entitled "Velocity Field Characteristics Of Minority Carriers (Electrons) In p-In.sub.o.53 Ga.sub.0.47 As" for a description of measured values of electron mobility and saturation velocity applicable to the III-V materials in field effect transistor (FET) applications useful in practicing the present invention. It is also known how to construct FET devices formed of a ternary material using oxide gates. See an article in the RCA Review, Vol. 42, Dec. 1981, pp. 542-556, by P. D. Gardner et al. entitled "Ga.sub.0.47 In.sub.0.53 As Metal Insulator Field-Effect Transistors (MISFETs) For Microwave Frequency Applications" for a description for constructing FETs with such oxide gates, particularly in metal insulator field-effect transistors (MISFETs) for microwave frequency applications. The provision of oxide gates in ternary material devices permits the direct coupling of logic gates to simplify thereby the design of circuits. The number of transistors per gate that are needed is greatly reduced using direct coupling logic design.
Despite the attractiveness of ternary material for devices, the design of logic gates utilizing this material has been found to be significantly different from either silicon or GaAs integrated circuits. The speed of operation of any logic gate depends, for the most part, on both the current drive capability of the driven stage and the capacitive loading presented at the output terminals. While a device formed of GaInAs material should be superior in speed to a silicon device of the same dimension, I have discovered, however, that undesirably excessive capacitive loading adversely affecting the operation speed occurs at the output terminals. The capacitive loading is due to the inherent development of an N/P junction. The capacitance of such an N/P junction is so large that it would appear to dominate any additional gate loads that may be connected to the output.
To further complicate this undesirable excessive capacitive effect, I further discovered that if two input driver transistors are connected in parallel to produce an "OR" function, the N+/P junction capacitance will be doubled, further slowing the speed of operation of the logic gate. Unfortunately, the P type layers useful for such devices are required to be relatively highly doped, usually of the order of about 3.times.10.sup.16 cm.sup.-3. Such high doping causes the N+/P junction to have a smaller depletion width and a larger capacitance.